ARCHITECTURE Datasheet(PDF) - CY7C1350B

Fabricant	No de pièce	Fiches technique	Description
Cypress Semiconductor	CY7C1350B	200Kb/14P	128Kx36 Pipelined SRAM with NoBL Architecture
	CY7C1353B	535Kb/15P	256Kx18 Flow-Through SRAM with NoBL Architecture
	CY7C1352	187Kb/12P	256K x18 Pipelined SRAM with NoBL Architecture
	CY7C1353	162Kb/13P	256Kx18 Flow-Through SRAM with NoBL Architecture
	CY28416	276Kb/15P	Next Generation FTG for Intel-R Architecture
	CY7C1333	183Kb/12P	64Kx32 Flow-Thru SRAM with NoBL??Architecture
	CY7C1351	185Kb/13P	128Kx36 Flow-Through SRAM with NoBL TM Architecture
	CY7C1352G	223Kb/13P	4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture
	CY7C1352F	291Kb/13P	4-Mbit (256Kx18) Pipelined SRAM with NoBL??Architecture
	CY7C1352B	189Kb/12P	256K x 18 Pipilined SRAm with NoBL Architecture
	CY7C1310KV18	1Mb/32P	18-Mbit QDR짰 II SRAM Two-Word Burst Architecture
	CY7C1317KV18	1Mb/33P	18-Mbit DDR II SRAM Four-Word Burst Architecture
	CY7C1317CV18	696Kb/31P	18-Mbit DDR-II SRAM 4-Word Burst Architecture
	CY7C1511KV18	837Kb/31P	72-Mbit QDR II SRAM 4-Word Burst Architecture
	CY7C1416BV18	672Kb/29P	36-Mbit DDR-II SRAM 2-Word Burst Architecture
	CY7C1416JV18	630Kb/26P	36-Mbit DDR-II SRAM 2-Word Burst Architecture
	CY7C1312BV18	1Mb/29P	18-Mbit QDR짰 II SRAM Two-Word Burst Architecture
	MB91460H	9Mb/105P	32-bit RISC, load/store architecture, five-stage pipeline
	MB91F465KA	2Mb/86P	32-bit RISC, load/store architecture, five-stage pipeline
	CY7C1316BV18	257Kb/24P	18-Mbit DDR-II SRAM 2-Word Burst Architecture

ARCHITECTURE Fiches technique, PDF